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| NTHD2110T Power MOSFET -12 V, -6.4 A, Single P-Channel +TVS, ChipFETt Package Features AND PIN A * Low RDS(on) MOSFET and TVS Diode ChipFET Package * Integrated Drain Side TVS for 15 kV Contact Discharge ESD * * Protection 1.8 V Gate Rating This is a Pb-Free Device V(BR)DSS http://onsemi.com RDS(on) MAX 40 mW @ -4.5 V -12 V 53 mW @ -2.5 V 80 mW @ -1.8 V -6.4 A ID MAX Applications * Battery Switch and Load Management Applications in Portable Equipment MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (Note 1) Steady State t5s Power Dissipation (Note 1) Steady State t5s Operating Junction and Storage Temperature Storage Temperature Range Lead Temperature for Soldering Purposes (1/8 from case for 10 seconds) TJ, TSTG TJ TL TA = 25C TA = 85C TA = 25C PD TA = 25C 2.3 -55 to 150 -55 to 150 260 C C C Symbol VDSS VGS ID Value -12 "8 -4.5 -3.2 -6.4 1.1 W Unit V V A TVS VRWM 12 S VC @ MAX IPP 21.5 IPP MAX 6.2 A A G D P-Channel MOSFET C TVS Diode 8 TVS MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Peak Power Dissipation 8 x 20 ms Double Exponential Waveform (Note 2) Human Body Model (HBM) Machine Model (MM) IEC 61000-4-2 Specification (Contact) Symbol PPK Value 150 Unit W ChipFET CASE 1206A STYLE 6 1 PIN CONNECTIONS 1 8 MARKING DIAGRAM 1 FTZ M G 2 3 4 8 7 6 5 ESD 16 400 30 kV V kV A 2 7 C/D D 6 D D 3 THERMAL RESISTANCE RATINGS Parameter Junction-to-Ambient - Steady State (Note 1) Junction-to-Ambient - t 5 s (Note 1) Symbol RqJA RqJA Max 110 55 C/W Unit D S 4 5 G FTZ M G Junction-to-Ambient - Steady State Min Pad 225 RqJA (Note 3) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Nonrepetitive Current Pulse per Figure 11. 3. Surface Mounted on FR4 board using 1 in sq size (Cu area = 1.127 in sq [1 oz] included traces). = Specific Device Code = Month Code = Pb-Free Package ORDERING INFORMATION Device NTHD2110TT1G Package ChipFET (Pb-Free) Shipping 3000/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2008 1 March, 2008 - Rev. 0 Publication Order Number: NTHD2110T/D NTHD2110T ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Zero Gate Voltage Drain Current V(Br)DSS IDSS VGS = 0 Vdc, ID = -250 mA VDS = -12 V, VGS = 0 V TJ = 25C TJ = 85C -12 -1.0 -5.0 "0.1 mA V mA Symbol Test Condition Min Typ Max Unit Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 6) Gate Threshold Voltage Drain-to-Source On-Resistance IGSS VDS = 0 V, VGS = "8.0 V VGS(th) RDS(on) VDS = VGS, ID = -250 mA VGS = -4.5 V, ID = -6.4 A VGS = -2.5 V, ID = -2.0 A VGS = -1.8 V, ID = -1.7 A -0.40 33 42 57 13.7 -0.85 40 53 80 V mW Forward Transconductance gFS VDS = -5.0 V, ID = -6.4 A S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge SWITCHING CHARACTERISTICS (Note 7) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time DRAIN-SOURCE DIODE CHARACTERISTICS Diode Forward Voltage VSD IS = -1.7 A, VGS = 0 V TJ = 25C TJ = 125C -0.7 -0.6 41.7 22 ns nC -1.0 V td(on) tr td(off) tf VDD = -6.0 V, VGS = -4.5 V, ID = -1.0 A, RG = 6.0 W 7.5 8.6 99.7 49.8 ns Ciss Coss Crss QG(TOT) QG(TH) QGS QGD VGS = -4.5 V, VDS = -6.0 V, ID = -6.4 A VDS = -6.0 V, VGS = 0 V f = 1.0 MHz 1072 260 134 10.5 0.6 1.3 2.8 14 nC pF Reverse Recovery Time Reverse Recovery Charge 4. 5. 6. 7. tRR QRR VGS = 0 V, dIS / dt = 100 A/ms, IS = -1.7 A VGS = 0 V, dIS / dt = 100 A/ms, IS = -1.7 A Surface Mounted on FR4 board using 1 in sq size (Cu area = 1.127 in sq [1 oz] included traces). Surface mounted on FR4 board using the minimum recommended pad size. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTHD2110T ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic TVS DIODE Reverse Working Voltage (Note 8) Breakdown Voltage (Note 9) Reverse Leakage Current Clamping Voltage (Note 10) Clamping Voltage (Note 10) Maximum Peak Pulse Current (Note 10) Capacitance VRWM VBR IR VC VC IPP CJ IT = 1 mA VRWM = 12 V IPP = 1 A (8 x 20 ms Waveform) IPP = 5 A (8 x 20 ms Waveform) 8 x 20 ms Waveform VR = 0 V, f = 1 MHz (Anode-to-GND) 12 14.5 0.6 15.7 10 15.7 19.1 6.2 60 V V nA V V A pF Symbol Test Condition Min Typ Max Unit 8. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 9. VBR is measured at pulse test current IT. 10. Pulse waveform per Figure 11. http://onsemi.com 3 NTHD2110T TYPICAL MOSFET PERFORMANCE CURVES 14 12 -ID, DRAIN CURRENT (A) 10 8 6 -1.4 V 4 -1.2 V 2 VGS = -1 V 0 0 0.5 1 1.5 2 2.5 -VDS, DRAIN-TO_SOURCE VOLTAGE (V) 3 0 0 0.5 1 1.5 2 -VGS, GATE-TO_SOURCE VOLTAGE (V) 2.5 -7 V -4.5 V -2.5 V -2 V -1.6 V TJ = 25C -1.8 V -ID, DRAIN CURRENT (A) 10 12.5 VDS w -10 V 7.5 5 25C 2.5 TJ = -55C 125C Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.38 0.34 0.3 0.26 0.22 0.18 0.14 0.1 0.6 0.2 1 3 4 5 -VGS, GATE-TO_SOURCE VOLTAGE (V) 2 6 ID = -6.4 A TJ = 25C 0.05 TJ = 25C 0.045 VGS = -2.5 V 0.04 0.035 VGS = -4.5 V 0.03 2 3 4 5 -ID, DRAIN CURRENT (A) 6 7 Figure 3. On-Resistance vs. Gate Voltage Figure 4. On-Resistance vs. Drain Current and Gate Voltage 100000 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 150 ID = -6.4 A VGS = -4.5 V VGS = 0 V -IDSS, LEAKAGE (nA) TJ = +150C 10000 TJ = +125C 1000 100 2 3 4 5 6 7 8 9 10 11 -VDS, DRAIN-TO_SOURCE VOLTAGE (V) 12 Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current http://onsemi.com 4 NTHD2110T 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 2 4 4.5 TTJ==25C 25C J VGS = 0 V CISS -VGS, GATE-TO-SOURCE VOLTAGE (V) 4 3.5 3 2.5 2 Q1 1.5 1 0.5 0 0 2 4 6 8 10 Qg, TOTAL GATE CHARGE (nC) 12 ID = -6.4 A TJ = 25C Q2 QT C, CAPACITANCE (pF) COSS CRSS 6 8 10 -VDS, DRAIN-TO_SOURCE VOLTAGE (V) 12 Figure 7. Capacitance Variation 1000 -IS, SOURCE CURRENT (A) VDS = -6 V ID = -1 A VGS = -4.5 V t, TIME (ns) 100 6 5 4 3 2 1 0 1 10 RG, GATE RESISTANCE (W) 100 0 Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge VGS = 0 V TJ = 25C td(off) tf tr 10 td(on) 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -VSD, SOURCE-TO-DRAIN VOLTAGE (V) 1 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current TYPICAL TVS PERFORMANCE CURVES 110 IPP, PEAK PULSE CURRENT (A) % OF PEAK PULSE CURRENT 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 t, TIME (ms) 20 25 30 td = IPP/2 c-t WAVEFORM PARAMETERS tr = 8 ms td = 20 ms 7 6 5 4 3 2 1 0 14 PULSE WAVEFORM 8 x 20 ms per Figure 11 15 16 17 18 VC, CLAMPING VOLTAGE (V) 19 20 Figure 11. Pulse Waveform, 8 x 20 ms Figure 12. Clamping Voltage vs Peak Pulse Current http://onsemi.com 5 NTHD2110T 18 16 16.5 14 12 IR, (nA) VZ, (V) 10 8 6 4 14.5 2 0 -60 -20 20 60 100 140 180 14 -60 16 15.5 15 IZ = 5 mA IZ = 1 mA 17 -10 40 90 140 190 TEMPERATURE (C) TEMPERATURE (C) Figure 13. Typical Leakage vs. Temperature Figure 14. Typical VZ @ 1 mA vs. Temperature 60 25C 50 C, CAPACITANCE (pF) 40 30 20 10 0 0 2 4 6 8 10 12 14 VBIAS, (V) Figure 15. Capacitance vs. VBIAS Gate Controller Input Voltage Load Figure 16. Typical Application Circuit http://onsemi.com 6 NTHD2110T PACKAGE DIMENSIONS ChipFETt CASE 1206A-03 ISSUE J D 8 7 6 5 q L 5 6 3 7 2 8 1 HE 1 2 3 4 E 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A b c D E e e1 L HE q MIN 1.00 0.25 0.10 2.95 1.55 MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5 NOM MIN 0.039 0.010 0.004 0.116 0.061 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.011 0.014 0.071 0.075 5 NOM MAX 0.043 0.014 0.008 0.122 0.067 e1 e b c A 0.05 (0.002) 0.017 0.079 SOLDERING FOOTPRINT* 2.032 0.08 1 STYLE 6: PIN 1. ANODE 2. DRAIN 3. DRAIN 4. GATE 5. SOURCE 6. DRAIN 7. DRAIN 8. CATHODE / DRAIN 2.362 0.093 0.635 0.025 PITCH 8X 8X 0.457 0.018 0.66 0.026 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ChipFET is a trademark of Vishay Siliconix ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 7 NTHD2110T/D |
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